JP-A No. 46143/1995 shows an example of a reset system in a case of a parallel to serial conversion circuit and a series to parallel conversion circuit. Particularly, FIG. 1 discloses a system of sending a reset signal to a first parallel to serial conversion circuit and sending the reset signal synchronized in the first parallel to serial conversion circuit sequentially to second and third parallel to serial conversion circuits thereby conducting resetting while sequentially synchronizing all of the parallel to serial conversion circuit.